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Standard ICs
ID ROM for CRT displays supporting plug & play
BU9881 / BU9881F
The BU9881 / BU9881F is a 1k bit EEPROM conforming to the standardized interface that enables Plug & Play on CRT displays.
*Applicationsdisplays Desktop CRT
Desktop LCD displays Other desktop PC displays External CRT displays for notebook computers
*Features EEPROM with configuration of 128 1) 1kbit serial
words x 8 bits. 2) Supports I2C bus. 3) Supports DDC1TM/ DDC2TM interfaces for monitor IDs. DDC is a registered trademark of VESA.
4) Supports clock frequencies of 100kHz and 400kHz. 5) Switching from DDC2 to DDC1 enabled using mode pin.
*Absolute maximum ratings (Ta = 25C)
Parameter Applied voltage Power dissipation BU9881 BU9881F Tstg Topr -- Symbol VCC Pd Limits - 0.3 ~ + 6.5 5001 3502 - 65 ~ + 125 - 40 ~ + 85 - 0.3 ~ VCC + 0.3 Unit V mW C C V
Storage temperature Operating temperature Voltage for various pins
1 Reduced by 5.0mW for each increase in Ta of 1C over 25C. 2 Reduced by 3.5mW for each increase in Ta of 1C over 25C. If input exceeds the absolute maximum ratings, the device may break down.
*Recommended operating conditions
Parameter Power supply voltage Input voltage Symbol VCC VIN Limits 2.7 ~ 5.5 0 ~ VCC Unit V V
1
Standard ICs
BU9881 / BU9881F
*Block diagram
MODE 1 7bit Address decoder Slave-word address register 1,024 bit EEPROM Array 8 8bit VCC
N.C.
2
7bit
Data register
7
VCLK
START N.C. 3 Control circuit
STOP 6 SCL
GND
4
High voltage generator
Power supply voltage detection
ACK
5
SDA
*Pin descriptions
Pin No. 1 2, 3 4 5 6 7 8 Pin name MODE N.C. GND SDA SCL VCLK VCC I/O I -- -- I/O I I -- Function Transmit-only mode switching pin (pulled down when used in open state) Not connected Reference voltage of 0V for all input / output Slave and word address serial data input / output Serial clock input pin for I2C mode Clock input pin for transmit-only mode Connect the power supply
The SDA pin is Nch open drain output, and should be used with an external pull-up resistor added.
2
Standard ICs
BU9881 / BU9881F
*Electrical characteristics (unless otherwise noted, Ta = - 40 to + 85C, Vcc = 2.7V to 5.5V)
Parameter Input high level voltage 1 Input low level voltage 1 Input high level voltage 2 Input low level voltage 2 Input high level voltage 3 Input low level voltage 3 Output low level voltage Input leakage current 1 Input leakage current 2 Output leakage current Operating current consumption Standby current Symbol VIH1 VIL1 VIH2 VIL2 VIH3 VIL3 VOL ILI1 ILI2 ILO ICC ISB Min. 0.7VCC -- 2.0 -- -- 0.8VCC -- -- -1 -1 -1 -- -- Max. -- 0.3VCC -- 0.8 0.4 -- 0.4 0.4 1 15 1 3 30 Unit V V V V V V V A A A mA A Conditions (SCL, SDA) (SCL, SDA) (VCLK) VCC = 4.5 ~ 5.5V (VCLK) VCC = 2.7 ~ 4.5V (VCLK) (MODE) (MODE) IOL = 3.0mA(SDA) VIN = 0V ~ VCC (SCL * SDA * VCLK) VIN = 0V ~ VCC (MODE) VOUT = 0V ~ VCC (SDA) VCC = 5.5V, tWR = 10ms VCC = 5.5V, MODE = GND VCLK * SDA * SCL = VCC Measurement Circuit -- -- -- -- -- -- Fig.1 Fig.2 Fig.2 Fig.2 Fig.3 Fig.4
*Measurement circuits
VCC VCC VCC 3.0mA ILO ILI VCC MODE, VCLK SDA, SCL
SDA
A V
VOL VOUT = 0 ~ VCC VIN = 0 ~ VCC
GND
GND
Data set when output is LOW
Fig. 1 LOW output voltage measurement circuit
VCC
Fig. 2 Input / output leakage current measurement circuit
VCC
A
VCC
ICC
VCC
A
VCC
ISB
100 / 400 kHz clock Write / read input
SCL, VCLK
SCL SDA VCLK
MODE
SDA MODE
VCC
GND
GND
Fig. 3 Current consumption measurement circuit
Fig. 4 Standby current measurement circuit
3
Standard ICs
BU9881 / BU9881F
*Operation timing characteristics (unless otherwise noted, Ta = - 40 to + 85C)
Parameter Clock frequency Data clock HIGH time Data clock LOW time SDA / SCL rise time SDA / SCL fall time Start condition hold time Start condition setup time Input data hold time Input data setup time Output data delay time Output data hold time Stop condition setup time Bus release time prior to start of transfer Internal write cycle time Effective noise elimination interval (SCL, SDA pins) Symbol f SCL t HIGH t LOW tR tF t HD: STA t SU: STA t HD: DAT t SU: DAT t PD t DH t SU: STO t BUF t WR tI Standard Mode VCC = 2.7 ~ 5.5V Min. 0 4.0 4.7 -- -- 4.0 4.7 0 250 0 0 4.7 4.7 -- -- Max. 100 -- -- 1.0 1.0 -- -- -- -- 3.5 -- -- -- 10 -- High-speed Mode VCC = 4.5 ~ 5.5V Min. 0 0.6 1.3 -- -- 0.6 0.6 0 100 0 0 0.6 1.3 -- -- Max. 400 -- -- 0.3 0.3 -- -- -- -- 0.9 -- -- -- 10 50 kHz s s s s s s ns s s s s s ms ns Unit
*Transmit - only MODE
Parameter VCLK output delay time VCLK HIGH time VCLK LOW time Mode transition time Power up time for transmission Symbol TVAA TVHIGH TVLOW TVHZ TVPU Standard Mode VCC = 2.7 ~ 5.5V Min. -- 4.0 4.7 -- 0 Max. 500 -- -- 500 -- High-speed Mode VCC = 4.5 ~ 5.5V Min. -- 0.6 1.3 -- 0 Max. 500 -- -- 500 -- ns s s ns ns Unit
4
Standard ICs
BU9881 / BU9881F
*Circuit operation
Basic operation The BU9881 / BU9881F is equipped with two modes, a normal I2C bus mode (bi-directional mode) and a transmitonly mode. * The transmit-only mode can be accessed by turning on the power supply to the IC, or by using the software to control the mode. In this mode, operation is synchronized to the clock input to VCLK, and it is possible to read the contents of the EEPROM memory from the SDA pin. * To switch from the transmit-only mode to the I2C bus mode, the clock signal that recognizes the switching of HIGH to LOW is input to the SCL pin. The I2C bus mode is effective following the edge of that clock. * To switch from the I2C bus mode to the transmit-only mode, the software can be used to control the mode, or the power supply to the IC can be turned off and then on again. This switches back to the transmit-only mode.
(1) Description of mode pin functions As shown in the illustration below, the software can be used to control the mode pin, enabling switching from the I2C bus mode to the transmit-only mode.
Set HIGH for 2s or longer Set LOW for 2s or longer
MODE
SCL
I2C MODE
TRANSMIT ONLY MODE
I2C MODE
Fig. 5
1)Transmit-only mode * This command causes all of the data written to the EEPROM to be read. After the transmit-only mode is entered, inputting the VCLK clock causes the data to be read from the SDA pin. * The SDA pin is in the "Hi-Z" state for the first nine clock signals input, and data is output sequentially, timed to the rise of the clock starting with the tenth clock. * Addresses are incremented automatically as clock pulses continue to be input to VCLK, with the data from the next address being read in sequence. While this is being done, the null bit (HIGH data) is output between the data of one address and that of the next address. * When the power supply is turned on, and when the mode is switched from the I2C bus mode to the transmit-only mode, the output data for the transmit-only mode is synchronized to VCLK as follows: Last address data0h address data1h address data and is incremented in sequence. (Following the last address, processing shifts to the 0h address.) Note: Reading in the transmit-only mode should not be done until the power supply has stabilized. When switching from the transmit-only mode to the I2C bus mode, assure the TVHZ time before beginning communications.
5
Standard ICs
BU9881 / BU9881F
VCC
SCL
VCLK TVPU SDA MODE Don't Care
1
2 TVAA HIGH-Z
9
10
D7
D0 NULL D7 bit 0h address
Last address
Fig. 6
2) I2C bus mode 1. Start condition (start bit recognition) * Before executing the various commands, if SDA is HIGH, a start condition (start bit) must be in effect such that SDA changes from HIGH to LOW. * This IC constantly detects whether or not the start condition (start bit) is fulfilled for the SDA and SCL lines. If this condition is not fulfilled, no commands will be executed. (Refer to the section on synchronized data input / output timing.) 2. Stop condition (stop bit recognition) * When the various commands have been completed, a stop condition (stop bit) can be used to terminate the commands by raising SDA from LOW to HIGH if SCL is HIGH. (Refer to the section on synchronized data input / output timing.) 3. Precautions concerning the write command The stop bit cannot be executed in the write mode, so data that has been transmitted cannot be written to the memory. 4. Write protect In the I2C bus mode, the VCLK pin can be used as a write protect control pin. When the VCLK pin is HIGH, the byte write and page write commands function, but when the VCLK pin is LOW, these two writing commands are canceled.
6
Standard ICs
BU9881 / BU9881F
(2) Device addressing * The master address should be output first, followed by the start condition, and then the slave address. * The first four bits of the slave address are used to recognize the device type. The device code for this IC is fixed at "1010". * The next three bits of the slave address may be either HIGH or LOW. * The last bit of the slave address (R / W: READ / WRITE) is used to specify either writing or reading, and is as shown below.
R / W set to 0: Writing (0 is also set in order to specify a word address for random reading.) R / W set to 1: Reading
1010
x
x
x
R/W
x: Don't
Care
(3) ACK signal * This acknowledge signal (ACK signal) is determined by the software, and indicates whether or not the data has been correctly transmitted. Regardless of whether the address is a master or slave address, the device on the transmitter (sending signal) side (the -com when a slave address is input for a write command or a read command, and this IC when read command data is output) opens the bus after this 8-bit data is output. * With a device on the receiving (reception) side (this IC when a slave address is input for a read command or write command, and a microcomputer when data is output for a read command), SDA is set to LOW during the nine-clock cycle, and the acknowledge signal (ACK signal) is output when 8-bit data is received. * This IC output the acknowledge signal (ACK signal) in the LOW state after a start condition and a slave address (8 bits) have been recognized. * For other writing operations, the acknowledge signal (ACK signal) is output in the LOW state each time that 8-bit data (word address or write data) is received. * In the various reading operations, 8-bit data (read data) is output, and then the acknowledge signal (ACK signal) in the LOW state is detected. If the acknowledge signal (ACK signal) is detected and no stop condition is sent from the master (microcomputer) side, this IC continues to output data. If the acknowledge signal (ACK signal) is not detected, this IC interrupts the transmission of data, recognizes a stop condition (stop bit), and terminates the reading operation. The IC then enters the standby mode. (Refer to "Fig. 7 acknowledge signal (ACK signal) response.")
Start condition
SCL (from -COM)
1
8
9
SDA (-COM output data)
SDA (data output from this IC) Acknowledge signal (ACK signal)
Fig. 7 Acknowledge signal (ACK signal) response (When slave address is input for writing or reading)
7
Standard ICs
BU9881 / BU9881F
*I C synchronous data input / output timing
2
tR SCL
tF
t HIGH
t LOW t HD: STA SDA (input) t BUF SDA (output) t PD t DH t SU: DAT
t HD: DAT
Fig. 8
SCL t SU: STA t HD: STA t SU: STO
SDA START BIT STOP BIT
Fig. 9
* Reading of input is done at the rising edge of SCL. * Output of data is synchronized to the falling edge of SCL.
*Write cycle timing
MODE "L" VCLK "H" SCL H SDA L D0 ACK t WR
Write data (n address)
Stop condition
Start condition
Fig. 10 Write cycle timing
8
Standard ICs
BU9881 / BU9881F
*Timing charts (1) Write cycle
MODE "L" VCLK "H" Start condition 1 SCL 8 9 17 18 26 Stop condition 27
SDA
1
0
1
0
0
0
0
0
0
x
WA6 Word address
WA0
D7 Write data
D0
Slave address
ACK signal (output)
x: Don't
Care
Fig. 11 Byte write cycle
1) Data is written to the address specified by the word address (n address). 2) After 8 bits of data are input, a stop bit is generated. This initiates writing of the data to the memory cell.
MODE "L" VCLK "H"
Start condition 9 18 27
Stop condition 54
SCL
SDA
1
0
1
0
0
0
0
0
0
x
WA6 Word address
WA0
D7 Write data
D0
D7 Write data
D0
Slave address
n+7 ACK signal (output)
x: Don't
Care
Fig. 12 Page write cycle
3) This command enables writing of 8 bytes of data. 4) This page write command is used to specify any of the first four bits (WA6 to WA3) of the word address. The address is incremented internally, and up to 8 bytes of data can be written to the last three bits (WA2 to WA0).
9
Standard ICs
(2) Read cycle
MODE "L" VCLK Don't Care Start condition
BU9881 / BU9881F
Stop condition
SCL
1
8
9
18
SDA
1
0
1
0
0
0
0
1
D7
D6
D5 Read data
D2
D1
D0
1
Slave address
ACK signal (output)
ACK signal (input)
Fig. 13 Current read cycle
1) With this IC, an internal address counter circuit increments the address one address at a time, and stores in memory the last word address (n address) for which the Write or read command was executed. 2) This command reads only the data of the word address (n +1 address) following the last word address to be written after the previous command has been executed. 3) If the ACK signal LOW following D0 is detected and no stop condition is sent from the master (microcomputer) side, reading can be continued sequentially to the data of the next word address. [The entire 1 kilobit (128 words) can be read.] (Refer to "Fig. 15 Sequential read cycle.") 4) To terminate this command, HIGH is input for the ACK signal following D0, and the SDA signal rises at the HIGH state of the SCL signal (stop condition), terminating the command.
MODE"L" VCLK Don't Care Start condition Start condition Stop condition
SCL
SDA
1
0
10
0
0
0
0
0
x
WA6 Word address
WA0
1
0
10
0
0
0
1
D7 Read data
D0
1
Slave address
Slave address ACK signal (output)
ACK signal (input)
Fig. 14 Random read cycle
5) This command enables reading of the data at the specified word address. 6) If the ACK signal LOW following D0 is detected and no stop condition is sent from the master (microcomputer) side, reading can be continued sequentially to the data of the next word address. [The entire 1 kilobit (128 words) can be read.] (Refer to "Fig. 15 Sequential read cycle.") 7) To terminate this command, HIGH is input for the ACK signal following D0, and the SDA signal rises at the HIGH state of the SCL signal (stop condition), terminating the command.
10
Standard ICs
BU9881 / BU9881F
MODE "L" VCLK Don't Care Start condition
Stop condition
SCL
SDA
1
0
1
0
0
0
0
1
D7 Read data
D0
D7 Read data
D0
Slave address
n+a ACK signal (output) ACK signal (input)
Fig. 15 Sequential read cycle (Example: For current reading)
8) If the ACK signal LOW following D0 is detected and no stop condition is sent from the master (microcomputer) side, reading can be continued sequentially to the data of the next word address. [The entire 1 kilobit (128 words) can be read.] 9) To terminate this command, HIGH is input for the ACK signal following any D0, and the SDA signal rises at the HIGH state of the SCL signal (stop condition), terminating the command. 10) Sequential reading is also possible with random reading. 11) With earlier ICs, switching from the DDC1 (transmit-only) mode to the DDC2 (I2C bus) mode was possible only by turning off the power supply and then turning it on again. With the BU9881 / BU9881F, however, switching between the normal I2C bus mode and the transmit-only mode can be done by controlling the mode pin (pin 1).
1. Controlling the mode pin (pin 1) from the main controller As shown in the figure below, the mode pin can be controlled through the software to switch from the I2C bus mode to the transmit-only mode.
Set HIGH for 2s or longer
Set LOW for 2s or longer
MODE
SCL
I C MODE
2
TRANSMIT ONLY MODE
I C MODE
2
Fig. 16
11
Standard ICs
2. Controlling the mode pin (pin 1) through an attachment
BU9881 / BU9881F
Vcc
VCLK
SCL
SDA
As shown at the left, if there is no SCL input for approximately 2 seconds (min.) to 6 seconds (max.) after the DDC2 (I2C bus) mode has been terminated with the diode, resistor, and capacitor, the mode changes automatically to the DDC1 (transmit-only) mode.
MODE
N.C.
N.C.
GND
62k
100F
Fig.17
*External dimensions (Units: mm)
BU9881 BU9881F
9.3 0.3 6.5 0.3 8 5
5.0 0.2 8 6.2 0.3 4.4 0.2 5
1 0.51Min.
4 7.62
3.2 0.2 3.4 0.3
0.3 0.1
1.5 0.1
1
4
2.54
0.5 0.1 0 ~ 15
0.11
1.27
0.4 0.1
0.3Min. 0.15
DIP8
SOP8
12
0.15 0.1

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